Hereinafter, the operation of a conventional charge distribution type A/D converter will be described.
FIG. 9(a) is a block diagram illustrating an example of a conventional charge redistribution type A/D converter which is disclosed in Japanese Published Patent Application No. Hei. 5-259913.
The conventional A/D converter is provided with an analog input terminal 301, an analog reference power supply terminal 302, a controller 201, a comparator 237, a storage register 238, transfer gates 222˜232, capacitors 233˜236 constituting a capacitor array, inverters 202˜206, 208, 217˜221, and NAND circuits 207, 209˜216. The relative capacitance ratios between the respective capacitors 233 (capacitance C1), 234 (capacitance C2), 235 (capacitance C3), and 236 (capacitance C4) are determined as follows:C1:C2:C3:C4=1:½:¼:⅛
Next, a description will be given of the operation principle of the conventional charge redistribution type A/D converter, with reference to the block diagram of FIG. 9(a) and the timing charts of operation signals shown in FIG. 9(b).
Initially, during the sampling period, the output levels of control signals S1, S3, S5, S7 and S9 outputted from the controller 201 become “1”, whereby the transfer gates 225, 227, 229, 231, and 233 are turned on. On the other hand, the output levels of the control signals S2, S4, S6, and S8, and the output level of the inverter 221 become “0”, whereby the transfer gates 224, 226, 228, 230, and 222 are turned off. Then, an analog signal supplied through the analog input terminal 301 is transmitted through the transfer gates 223, 225, 227, 229, and 231, whereby charging or discharging to/from the capacitors 233, 234, 235, and 236 is carried out. Thereby, sampling of the analog value of the analog signal is carried out.
During the holding period that follows the sampling period, the output level of the control signals S1, S3, S5, S7, and S9 become “0”, and the transfer gates 225, 227, 229, 231, and 223 are turned off, whereby the charge stored during the sampling period is held by the capacitors 233, 234, 235, and 236. Assuming that the level of the analog signal inputted to the analog input terminal 301 is V1, a voltage V at a comparison line, which is input to the comparator 237 at this time, is represented as follows:V=V1
Next, A/D conversion takes place. Initially, in the first state of A/D conversion, the output level of the control signal S3 outputted from the controller 201 becomes “1”, and the transfer gate 225 is turned on. Thereby, the level of a reference voltage Vr supplied from the analog reference power supply terminal 302 is applied to an end of the capacitor 233. Since the capacitance C1 of the capacitor 233 is about ½ of the sum of the capacitances of the capacitors C1˜C4, the voltage V at the comparison line that is input to the comparator 237 is represented as follows:V=−V1+Vr/2
When V<0, the output level of the comparator 237 which is transmitted to the controller 201 becomes “0”, and the output level of the control signal S3 outputted from the controller 201 is maintained at “1”, whereby the transfer gate 225 remains in the ON state, and the most significant bit is set at “1”. Further, when V>0, the output level of the comparator 237 becomes “1”, and the output levels of the control signals S2 and S3 outputted from the controller 201 become “1” and “0”, respectively, whereby the transfer gate 224 is turned on while the transfer gate 225 is turned off, and the most significant bit is set at “0”. In FIG. 9(b), the most significant bit is set at “1” when the output level of the control signal S2 is “0” and the output level of the control signal S3 is “1”.
Next, the second bit from the most significant bit is determined. In the controller 201, the output level of the control signal S5 is “1”, and the transfer gate 227 is turned on, whereby the voltage V at the comparison line inputted to the comparator 237 becomes a voltage indicated by either of the following two formulae, depending on the state of the predetermined most significant bit.V=−V1+Vr/2+Vr/4 (the most significant bit is “1”)V=−V1+Vr/4 (the most significant bit is “0”)
In the timing charts shown in FIG. 9(b), since the most significant bit is set at “1”, the comparison line voltage V is represented as follows:V=−V1+Vr+Vr/4
Also in this case, the second bit from the most significant bit is set at “1” when V<0, and it is set at “0” when V>0, by the comparator 237 and the controller 201, as in the case of determining the most significant bit. Hereinafter, a similar procedure is repeated until the least significant bit is determined. When the least significant bit is determined, the analog signal is classified as any of eight states (1111)˜(0000). In the timing charts shown in FIG. 9(b), the analog signal is (1100) finally.
Next, in the state where the result of A/D conversion is written in the storage register 238, the result of A/D conversion is written in the storage register 238 through the controller 201. In this state, the level of an END signal that is outputted from the controller 201 and functions as a control signal for the storage register 238 becomes “1”, and the result of A/D conversion that is supplied from the controller 201 through the end signal to the storage register 238 is written in the storage register 238. Hereinafter, A/D conversion is repeatedly executed through the above-mentioned operation procedure, i.e., sampling, holding, A/D conversion, and storage into the register.
By the way, when the A/D converter continuously performs two times of 4-bit A/D conversion, there are two cases where the converted value changes from (0000) to (1111) and where it changes from (1111) to (1111). In the latter case, the capacitor must be fully charged from the state where it is not charged at all, in contrast to the former case. Therefore, the charging/discharging current excessively flows through the analog input terminal 301.
Therefore, particularly when the analog input terminal 301 is connected at high impedance, extra charging time for the capacitor is required. However, the sampling time is limited to the limited conversion time, and the charging/discharging time for the capacitor is in reverse proportion to a time constant of CR, and therefore, a resistance value that can be connected to the analog input terminal 301 is also limited.
However, in the conventional A/D converter shown in FIG. 9(a), reduction in sampling time is realized by using a technique described hereinafter, as a countermeasure against the above-mentioned limitations.
That is, in the state where A/D conversion is completed and the result of conversion is written in the storage register 238, the level of the END signal outputted from the controller 201 changes from “0” to “1”, and the result of A/D conversion is written in the storage register 238 under control of the END signal. Further, the output level of the inverter 206 changes from “1” to “0”, and the output levels of the NAND circuit 207 and 209˜216 become “1”, whereby the respective transfer gates 223, 224, 227, 229, 231, and 232 are turned off by the inversion functions of the inverters 208 and 217˜221. In this case, the total charge amount Q in the capacitors 233˜236 is initialized as follows.Q=C1·Vr
Therefore, during sampling in the next A/D conversion that follows the previous A/D conversion, all of the transfer gates 223, 225, 227, 229, 231, and 232 are turned on, and a voltage level Vo in the B line at the start of sampling is given as follows.Vo=Vr·C1/(C1+C2+C3+C4)=Vr/2
Accordingly, during sampling for the analog voltage applied to the analog input terminal 301 with respect to the capacitors 233˜236, since charging or discharging from the level of Vr/2 is constantly carried out regardless of the amount of charge that is sampled and held during the previous conversion, the length of the sampling period can be reduced to ½.
FIG. 9(c) is a block diagram illustrating another example of a conventional charge redistribution type A/D converter.
As shown in FIG. 9(c), the conventional A/D converter is provided with an analog input terminal 303, an analog reference power supply terminal 304, a controller 201, inverters 206, 208, 221, and 239, NAND circuits 207 and 240˜263, transfer gates 222˜232, capacitors 233˜236 constituting a capacitor array, a comparator 237, a storage register 238, an initial value setting register 264, and a decoder 265. As in FIG. 9(a), the relative capacitance ratios between the respective capacitors 233 (capacitance C1), 234 (capacitance C2), 235 (capacitance C3), and 236 (capacitance C4) are determined as follows:C1:C2:C3:C4=1:½:¼:⅛
Further, FIG. 9(d) illustrate timing charts indicating operation signals in FIG. 9(c).
Hereinafter, a description will be given of the operation of the conventional A/D converter with reference to the block diagram of FIG. 9(c) and timing charts of operation signals shown in FIG. 9(d).
As for the timings of the control signals S1˜S9 and the END signal which are outputted from the controller 201, these signals change as in the above-mentioned conventional A/D converter. During sampling, holding, and A/D conversion, the level of the END signal is “0”. Accordingly, the output level of the inverter 206 is “1”, and thereby the NAND circuits 256˜263 invert the output levels of the NAND circuits 240˜247 and output the inverted output levels, respectively. As a result, the output levels of the control signals S1˜S9 supplied from the controller 201 are outputted as they are. Accordingly, gate control for the transfer gates 224˜231 connected to the capacitors 233˜236 is carried out according to the control signals S1˜S9 outputted from the controller 201, as described for FIG. 9(a). Further, since gate control for the transfer gates 222 and 223 is carried out in like manner as described for FIG. 9(a), the series of operations from sampling to A/D conversion are carried out in the same procedure as described for FIG. 9(a).
The prior art shown in FIG. 9(c) differs from the prior art shown in FIG. 9(a) in the following points. When A/D conversion is completed, writing of the result of conversion into the storage register 238 takes place, and the level of the END signal outputted from the controller 201 changes from “0” to “1”. Then, the result of conversion supplied from the controller 201 to the storage register 238 is written in the storage register 238, and the output level of the inverter 206 changes from “1” to “0”, and thereby all of the output levels of the NAND circuits 207 and 240˜247 become “1”. As a result, the output level of the inverter 208 changes from “1” to “0”, and the output level of the inverter 239 changes from “0” to “1”, whereby the output levels of the NAND circuits 248˜255 are determined by the output of the decoder 265, i.e., the set value outputted from the initial value setting register 264.
As described above, the initial value setting register 264 enables the initial value setting register 264 to selectively set the amounts of initial charges to the capacitors 233˜236, i.e., the voltages of the capacitors 233˜236 at starting of sampling.
The initial set voltage may be arbitrarily determined within the minimum width of A/D conversion accuracy.
However, the prior arts described with reference to FIGS. 9(a) and 9(b) need many inverters and gates for setting the initial voltage, and the numbers of inverters and gates dramatically increase as the number of bits of the A/D converter increases. Further, the degree of freedom in setting the initial voltage is low.